1. Field of the Invention
The present invention relates to a microprocessor with an on-chip cache memory and an address translation buffer, and more particularly to a microprocessor of the kind which has at least a two-way set associative structure in a pipeline data processing system.
2. Description of the Prior Art
In the prior art there is known pipeline data processing system having a cache memory and an address translation buffer or translation lookaside buffer (TLB) for performing address translation from virtual to physical address.
FIG. 1 shows one example of a general construction of the pipeline data processing system according to the prior art. In the figure, the system consists of seven stages, from an instruction fetch stage (IF) to an operand storing stage (STORE). Namely, the pipeline system consists of an instruction fetch stage (IF) an instruction decode stage (ID), a virtual address calculation stage (OAG), an address translation stage (TLB), an operand read stage (TAG.DATA), an instruction execution stage (EXEC) and an operand storing stage (STORE).
FIG. 2 shows the detailed construction of the combined address translation stage TLB and the operand read stage TAG.DATA in the pipeline data processing system. In the figure, reference numeral 1 indicates a logical address register, 3 indicates a physical address register, 5 an address translation buffer (TLB), 7 the tag field of a two-way set associative cache memory, 9 the data field of the associative cache memory, 11 a comparator, 13 a selector and 19 a data sector.
In operation, each of the logical addresses 21 calculated in the stage OAG is registered in the logical address register 1. Among the logical addresses 21 thus registered in the address register 1, the number of bits corresponding to a page in a virtual memory (e.g., the upper 20 bits of, for instance, 32-bit processor), is applied to the address translation buffer 5, where they are translated into a 20-bit signal for the physical address 27. The upper 20 bits of the physical address 27 are registered in the upper 20-bit positions of the physical address register 3.
On the other hand, among the logical address bits registered in the logical address register 1, the remaining lower 12-bit address 25 is registered in the 12-bit position of the physical address register 3 without any change in the address translation. All of the above operations are performed in the stage TLB.
Description of the operations performed in the TAG.DATA will now be made. The TAG. DATA cache structure is two-way set associative and is composed of the tag field 7 having X and Y sections and the data field 9 also having X and Y sections.
In the X and Y sections of the data field 9 there is formed about 256 lines each having 4K bytes, constituting the total capacity of 8K bytes about the data field 9. Data is stored in the data field 9 with each line being one unit. Moreover, each line forms a single unit when it is desired to check by the comparator 11 whether or not data to be sought exists in the data field 9, the details of which will be described later.
Each line having the same number as that which can exist in the lines from 0 to 255 in the X and Y data field is selected using partial data in the logical address. When a target data held in the logical address register 1 exists in one of the two lines thus selected, it results in a cache hit. When the target data held in the logical address register does not exist in either of the two lines, it results in a miss.
On the other hand, in each of the X and Y sections of the tag field 7, there is provided 256 tags from 0 to 255 where each of the lines corresponding to the data cache 9 is retained. As one example of this attribute, it may be a valid bit which indicates whether or not the upper 20 bits of data stored in the physical address register 3 are also stored in the corresponding data cache 9. The reading-out of the target data from the data cache 9 is carried out in the following manner.
Each line having the same number is selected from each of the X and Y sections of the data field 9, and eight bits 29 with bit numbers ranging from 20 to 27 among the physical address are stored in the physical address register 3. The output signals 31 and 33 indicate these addresses selected, assuming that the most significant bit is equal to 0.
Moreover, the attributes relating to the lines thus read from the X and Y sections of the data field 9 are read from the tag field 7 by the eight-bit value 39 of the physical address retained in the physical address register 3, so as to produce either cache hit or miss. When a hit occurs, a determination is made as to whether the hit occurs in the lines 31 of the X section or in the lines 33 of the Y section of the data field 9, and the result of the determination (i.e., the output signal 43) is applied to a selector 13.
The selector 13 selects either one of the output signals 31 or 33, which has resulted in a cache hit, and its hit output signal 45 is applied to the data selector 19. The data selector 19 selects and produces necessary data 47 in accordance with the lower four bits of the physical address and the 16-byte size of the input signal 45, which is to be executed in the next execution stage EXEC in the pipeline data processing system.
As described in the above two-way set associative cache memory according to the prior art, the reading-out of data was carried out by electrically activating the data cache memory, regardless of cache hit or miss conditions. In addition, in the two-way set associative cache memory, the target data is actually held in one line in either one of the X or Y sections of the data field thus divided. Nevertheless, a plurality of the lines in the X and Y sections are activated for reading-out data.
The above problems become striking in the one-chip microprocessor having a two-way set associative cache in order to increase cache hit efficiency;
(1) In the one-chip microprocessor, it is extremely important to decrease the power consumption in order to decrease the heat generation and to lower the operation temperature, as well as to improving its reliability. However, when the multi-level cache memory mapping system such as a four-way set associative cache is employed, the data volume to be read out of the data field must be increased, which requires more time than that for the direct cache system. As a result, power consumption is also considerably increased for data read-out.
(2) Since the data read-out function is performed in the data field even in the case of a miss, it results in wasted power consumption for that operation, as well as a decrease the processing speed of the microprocessor because of time wasted on this useless operation. Specifically, since the size of the cache memory is limited in the microprocessor, the upper limit of the cache memory capacity that can be incorporated in the chip in these days is rather small, totaling about 8 k-bytes, and the miss rate in the cache memory can become as large as 10%.